FPGA-based accelerator for the verification of leading-edge wireless systems
Proceedings of the 46th Annual Design Automation Conference
A flexible layered architecture for accurate digital baseband algorithm development and verification
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
System level design tools for creating DSP designs reducethe amount of time needed to create a DSP design, inpart by eliminating the need for verification between systemmodel and hardware implementation. The design is developedwithin a high level modeling environment. This descriptionis compiled into a hardware description language,and synthesized by traditional FPGA tools. The use of systemlevel tools can eliminate the need for an extensive hardwareknowledge. This paper demonstrates how such toolscan be used to build a Bit Error Rate (BER) tester, andhow hardware co-simulation of the entire system provided a10,000x speed-up over a pure software simulation.