Fast pseudorandom generators for normal and exponential variates
ACM Transactions on Mathematical Software (TOMS)
Maximally equidistributed combined Tausworthe generators
Mathematics of Computation
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Toward Correctly Rounded Transcendentals
IEEE Transactions on Computers
Design of High Speed AWGN Communication Channel Emulator
Analog Integrated Circuits and Signal Processing
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Compact FPGA-based True and Pseudo Random Number Generators
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Continuous random variate generation by fast numerical inversion
ACM Transactions on Modeling and Computer Simulation (TOMACS)
A Gaussian Noise Generator for Hardware-Based Simulations
IEEE Transactions on Computers
MiniBit: bit-width optimization via affine arithmetic
Proceedings of the 42nd annual Design Automation Conference
Son of seminumerical algorithms
ACM SIGSAM Bulletin
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
A hardware gaussian noise generator using the wallace method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices
Journal of VLSI Signal Processing Systems
FPGA-optimised high-quality uniform random number generators
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel pseudorandom noise and band jammer generator using a composite sinusoidal function
IEEE Transactions on Signal Processing
An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A hardware efficient random number generator for nonuniform distributions with arbitrary precision
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
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We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples. The noise generator can be used as a key component in a hardware-based simulation system, such as for exploring channel code behavior at very low bit error rates, as low as 10^{-12} to 10^{-13}. The main novelties of this work are accurate analytical error analysis and bit-width optimization for the elementary functions involved in the Box-Muller method. Two 16-bit noise samples are generated every clock cycle and, due to the accurate error analysis, every sample is analytically guaranteed to be accurate to one unit in the last place. An implementation on a Xilinx Virtex-4 XC4VLX100-12 FPGA occupies 1,452 slices, three block RAMs, and 12 DSP slices, and is capable of generating 750 million samples per second at a clock speed of 375 MHz. The performance can be improved by exploiting concurrent execution: 37 parallel instances of the noise generator at 95 MHz on a Xilinx Virtex-II Pro XC2VP100-7 FPGA generate seven billion samples per second and can run over 200 times faster than the output produced by software running on an Intel Pentium--4 3 GHz PC. The noise generator is currently being used at the Jet Propulsion Laboratory, NASA to evaluate the performance of low-density parity-check codes for deep-space communications.