FPGA-optimised high-quality uniform random number generators

Authors:
David Barrie Thomas;Wayne Luk
Affiliations:
Imperial College, London, United Kingdom;Imperial College, London, United Kingdom
Venue:
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Year:
2008

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Abstract

This paper introduces a method of constructing random numbergenerators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. The construction methodis designed to ensure maximum clock rates, while using the minimum of resources, and providing statistical quality at the level of the best software generators. In all platforms tested, the generators are limited in speed only by the clock distribution network or the maximum clockspeed of the underlying RAM primitives, using a platform independent VHDL description with no placement or other hints. The area utilisation is also very low, with a Virtex-5 generator requiring just one Block-RAMand 41 slices to produce 48Gb/s at 550MHz: over 14 times faster than the commonly used Mersenne-Twister RNG on an Opteron at 2.2GHz, while providing the same level of quality