ACM Transactions on Modeling and Computer Simulation (TOMACS)
Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on uniform random number generation
Tables of maximally equidistributed combined LFSR generators
Mathematics of Computation
Improved long-period generators based on linear recurrences modulo 2
ACM Transactions on Mathematical Software (TOMS)
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices
Journal of VLSI Signal Processing Systems
FPGA-optimised high-quality uniform random number generators
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
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Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimized RNGs, so they are not commonly used in real-world designs. This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise XOR operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths. This provides a good resource-quality balance compared to previous FPGA-optimized generators, between the previous high-resource high-period LUT-FIFO RNGs and low-resource low-quality LUTOPT RNGs, with quality comparable to the best software generators. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within this paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in this paper, backed up by an online set of very high speed integrated circuit hardware description language (VHDL) generators and test benches.