High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
Journal of Signal Processing Systems
Hardware acceleration of matrix multiplication over small prime finite fields
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
The LUT-SR family of uniform random number generators for FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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FPGA-optimised Random Number Generators (RNGs) are more resource efficient than software-optimised RNGs, as they can take advantage of bit-wise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimised RNGs, so they are not commonly used in real-world designs. This paper describes a new type of FPGA RNG called a LUT-SR RNG, which takes advantage of bit-wise XOR operations and the ability to turn LUTs into shift-registers of varying lengths. This provides a good resource-quality balance compared to previous FPGA-optimised generators, between the previous high-resource high-quality LUT-FIFO RNGs and low-resource low-quality LUT-OPT RNGs. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within the paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in the paper, backed up by an online set of VHDL generators and test-benches.