FPGA-optimised high-quality uniform random number generators
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A hardware framework for the fast generation of multiple long-period random number streams
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
An FPGA implementation of a parallelized MT19937 uniform random number generator
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm
Journal of Signal Processing Systems
The LUT-SR family of uniform random number generators for FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.