An LSI random number generator (RNG)
Proceedings of CRYPTO 84 on Advances in cryptology
Handbook of Applied Cryptography
Handbook of Applied Cryptography
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
True Random Number Generator Embedded in Reconfigurable Hardware
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Compact FPGA-based True and Pseudo Random Number Generators
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable trusted computing in hardware
Proceedings of the 2007 ACM workshop on Scalable trusted computing
A hardware generator of multi-point distributed random numbers for Monte Carlo simulation
Mathematics and Computers in Simulation
FPGA-optimised high-quality uniform random number generators
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware architecture for trustable vehicular electronic control units
Proceedings of the 2009 International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly
Analysis and enhancement of random number generator in FPGA based on oscillator rings
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
High speed true random number generator based on open loop structures in FPGAs
Microelectronics Journal
Implementing true random number generators by generating crosstalk effects in FPGA chips
Proceedings of the 6th FPGAworld Conference
On-line sensing for healthier FPGA systems
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A cluster-based protocol for self-organizing UWB wireless ad hoc sensor networks
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Using Data Contention in Dual-ported Memories for Security Applications
Journal of Signal Processing Systems
A closer look at security in random number generators design
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
On the design of hardware building blocks for modern lattice-based encryption schemes
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics. We discuss the engineering challenges of extracting random bits from digital circuits, and we report the results of running standard statistical tests (NIST) on the output generated by our system.