An LSI random number generator (RNG)
Proceedings of CRYPTO 84 on Advances in cryptology
Handbook of Applied Cryptography
Handbook of Applied Cryptography
An embedded true random number generator for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
New Methods for Digital Generation and Postprocessing of Random Data
IEEE Transactions on Computers
A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks
IEEE Transactions on Computers
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices
Journal of VLSI Signal Processing Systems
Fast Digital TRNG Based on Metastable Ring Oscillator
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A novel cache architecture with enhanced performance and security
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Analysis and enhancement of random number generator in FPGA based on oscillator rings
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
High speed true random number generator based on open loop structures in FPGAs
Microelectronics Journal
Implementing true random number generators by generating crosstalk effects in FPGA chips
Proceedings of the 6th FPGAworld Conference
Improving the Robustness of Ring Oscillator TRNGs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A reconfigurable crypto sub system for the software communication architecture
MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
Evaluation of Random Delay Insertion against DPA on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
New high entropy element for FPGA based true random number generators
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Using Data Contention in Dual-ported Memories for Security Applications
Journal of Signal Processing Systems
A closer look at security in random number generators design
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor
Journal of Electronic Testing: Theory and Applications
A very high speed true random number generator with entropy assessment
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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This paper presents a new True Random Number Generator (TRNG) based on an analog Phase-Locked Loop (PLL) implemented in a digital Altera Field Programmable Logic Device (FPLD). Starting with an analysis of the one available on chip source of randomness - the PLL synthesized low jitter clock signal, a new simple and reliable method of true randomness extraction is proposed. Basic assumptions about statistical properties of jitter signal are confirmed by testing of mean value of the TRNG output signal. The quality of generated true random numbers is confirmed by passing standard NIST statistical tests. The described TRNG is tailored for embedded System-On-a-Programmable-Chip (SOPC) cryptographic applications and can provide a good quality true random bit-stream with throughput of several tens of kilobits per second. The possibility of including the proposed TRNG into a SOPC design significantly increases the system security of embedded cryptographic hardware.