Handbook of Applied Cryptography
Handbook of Applied Cryptography
True Random Number Generator Embedded in Reconfigurable Hardware
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
New Methods for Digital Generation and Postprocessing of Random Data
IEEE Transactions on Computers
A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks
IEEE Transactions on Computers
High-Speed True Random Number Generation with Logic Gates Only
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Fast Digital TRNG Based on Metastable Ring Oscillator
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Analysis and enhancement of random number generator in FPGA based on oscillator rings
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Observing the Randomness in RO-Based TRNG
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
A closer look at security in random number generators design
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
On the design of hardware building blocks for modern lattice-based encryption schemes
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
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We demonstrate a new high-entropy digital element suitable for True Random Number Generators (TRNGs) embedded in Field Programmable Gate Arrays (FPGAs). The original idea behind this principle lies in the randomness extraction on oscillatory trajectory when a bi-stable circuit is resolving a metastable event. Although such phenomenon is well known in the field of synchronization flip-flops, this feature has not been applied for TRNG designs. We propose a new bi-stable structure - Transition Effect Ring Oscillator (TERO) where oscillatory phase can be forced on demand and be reliably synthesized in FPGA. Randomness is represented as a variance of the TERO oscillations number counted after each excitation. Variance is highly dependent on the internal noise of logic cells and can be used easily for reliable instant inner testing of each generated bit. Our proposed mathematical model, simulations and hardware experiments show that TERO is significantly more sensitive to intrinsic noise in FPGA logic cells and less sensitive to global perturbations than a ring oscillator composed from the same elements. The experimental TERO-based TRNG passes NIST 800-22 tests.