True Random Number Generator Embedded in Reconfigurable Hardware
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Hardware Random Number Generator
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Design of Reliable True Random Number Generator for Cryptographic Applications
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
The bit extraction problem or t-resilient functions
SFCS '85 Proceedings of the 26th Annual Symposium on Foundations of Computer Science
Design of testable random bit generators
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
High-Speed True Random Number Generation with Logic Gates Only
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Post-Processing Functions for a Biased Physical Random Number Generator
Fast Software Encryption
Fast Digital TRNG Based on Metastable Ring Oscillator
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Mobile communication security controllers an evaluation paper
Information Security Tech. Report
Guest Editors’ Introduction to Security in Reconfigurable Systems Design
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Techniques for Design and Implementation of Secure Reconfigurable PUFs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Physical unclonable function and true random number generator: a compact and scalable implementation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Analysis and enhancement of random number generator in FPGA based on oscillator rings
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
High speed true random number generator based on open loop structures in FPGAs
Microelectronics Journal
Improving the Robustness of Ring Oscillator TRNGs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A meta-level true random number generator
International Journal of Critical Computer-Based Systems
New high entropy element for FPGA based true random number generators
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Implementation and testing of high-speed CMOS true random number generators based on chaotic systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
A comparison of post-processing techniques for biased random number generators
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
FPGA-Based true random number generation using circuit metastability with adaptive feedback control
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Secure random number generation in wireless sensor networks
Proceedings of the 4th international conference on Security of information and networks
Using Data Contention in Dual-ported Memories for Security Applications
Journal of Signal Processing Systems
Contactless electromagnetic active attack on ring oscillator based true random number generator
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
A closer look at security in random number generators design
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
Analog Integrated Circuits and Signal Processing
A holistic approach examining RFID design for security and privacy
The Journal of Supercomputing
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor
Journal of Electronic Testing: Theory and Applications
A very high speed true random number generator with entropy assessment
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
A novel design method for discrete time chaos based true random number generators
Integration, the VLSI Journal
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This paper is a contribution to the theory of true random number generators based on sampling phase jitter in oscillator rings. After discussing several misconceptions and apparently insurmountable obstacles, we propose a general model which, under mild assumptions, will generate provably random bits with some tolerance to adversarial manipulation and running in the megabit-per-second range. A key idea throughout the paper is the fill rate, which measures the fraction of the time domain in which the analog output signal is arguably random. Our study shows that an exponential increase in the number of oscillators is required to obtain a constant factor improvement in the fill rate. Yet, we overcome this problem by introducing a postprocessing step which consists of an application of an appropriate resilient function. These allow the designer to extract random samples only from a signal with only moderate fill rate and, therefore, many fewer oscillators than in other designs. Last, we develop fault-attack models and we employ the properties of resilient functions to withstand such attacks. All of our analysis is based on rigorous methods, enabling us to develop a framework in which we accurately quantify the performance and the degree of resilience of the design.