Communications of the ACM
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
True Random Number Generator Embedded in Reconfigurable Hardware
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Hardware Random Number Generator
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks
IEEE Transactions on Computers
High-Speed True Random Number Generation with Logic Gates Only
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
FPGA-Based true random number generation using circuit metastability with adaptive feedback control
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
A closer look at security in random number generators design
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
Comparison of self-timed ring and inverter ring oscillators as entropy sources in FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A Self-Timed Ring Based True Random Number Generator
ASYNC '13 Proceedings of the 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
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The proposed true random number generator (TRNG) exploits the jitter of events propagating in a self-timed ring (STR) to generate random bit sequences at a very high bit rate. It takes advantage of a special feature of STRs that allows the time elapsed between successive events to be set as short as needed, even in the order of picoseconds. If the time interval between the events is set in concordance with the clock jitter magnitude, a simple entropy extraction scheme can be applied to generate random numbers. The proposed STR-based TRNG (STRNG) follows AIS31 recommendations: by using the proposed stochastic model, designers can compute a lower entropy bound as a function of the STR characteristics (number of stages, oscillation period and jitter magnitude). Using the resulting entropy assessment, they can then set the compression rate in the arithmetic post-processing block to reach the required security level determined by the entropy per output bit. Implementation of the generator in two FPGA families confirmed its feasibility in digital technologies and also confirmed it can provide high quality random bit sequences that pass the statistical tests required by AIS31 at rates as high as 200 Mbit/s.