Communications of the ACM
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Predicting Performance of Micropipelines Using Charlie Diagrams
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Improving the Robustness of Ring Oscillator TRNGs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A very high speed true random number generator with entropy assessment
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where sources of randomness are very limited. Inverter Ring Oscillators (IRO) are relatively well characterized as entropy sources. However, it is known that they are very sensitive to working conditions. This fact makes them vulnerable to attacks. On the other hand, Self-Timed Rings (STR) are currently considered as a promising solution to generate robust clock signals. Although many studies deal with their temporal behavior and robustness in Application Specific Integrated Circuits (ASIC), equivalent study does not exist for FPGAs. Furthermore, these oscillators were not analyzed and characterized as entropy sources aimed at TRNG design. In this paper, we analyze STRs as entropy sources for TRNGs implemented in FPGAs. Next, we compare STRs and IROs when serving as sources of randomness. We show that STRs represent very interesting alternative to IROs: they are more robust to environmental fluctuations and they exhibit lower extra-device frequency variations.