True Random Number Generator Embedded in Reconfigurable Hardware
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Hardware Random Number Generator
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Compact FPGA-based True and Pseudo Random Number Generators
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An embedded true random number generator for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
New Methods for Digital Generation and Postprocessing of Random Data
IEEE Transactions on Computers
A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks
IEEE Transactions on Computers
Shift-register synthesis and BCH decoding
IEEE Transactions on Information Theory
Correlation-immunity of nonlinear combining functions for cryptographic applications (Corresp.)
IEEE Transactions on Information Theory
Analysis and enhancement of random number generator in FPGA based on oscillator rings
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Using Data Contention in Dual-ported Memories for Security Applications
Journal of Signal Processing Systems
A closer look at security in random number generators design
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
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Most hardware ''True'' Random Number Generators (trng) take advantage of the thermal agitation around a flip-flop metastable state. In Field Programmable Gate Arrays (fpga), the classical trng structure uses at least two oscillators, build either from pll or ring oscillators. This creates good trng albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This speed requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution protocols. The proposed architecture is very simple and generic as it is based on an open loop structure with no specific component such as pll.