A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks
IEEE Transactions on Computers
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
SeReCon: a secure reconfiguration controller for self-reconfigurable systems
International Journal of Critical Computer-Based Systems
Efficient implementation of true random number generator based on SRAM PUFs
Cryptography and Security
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Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile secret keys, whereas TRNGs are used for generating random padding bits, initialization vectors and nonces in cryptographic protocols. This paper proposes a scalable design technique to implement both a delay-based PUF and a jitter-based TRNG using ring oscillators. By sharing and reusing a significant amount of hardware resources, we achieve nearly 50% area reduction as compared to discrete implementations. We also propose and demonstrate a co-processor-based design that renders the circuit portable across various embedded processor platforms on FPGAs. Multiple scaled designs using 32 to 128 ring oscillators have been implemented and verified on Xilinx Spartan3S500E FPGA. A representative design uses 32 3-inverter ring oscillators, 64 flip-flops/latches, 31 2-input XOR gates and control circuitry giving a 3.2Mbps truly random stream and 31-bit unique device signature.