Communications of the ACM
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Computing: A New Business Model and its Impact on SoC Design
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Security in embedded systems: Design challenges
ACM Transactions on Embedded Computing Systems (TECS)
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable Security Support for Embedded Systems
HICSS '06 Proceedings of the 39th Annual Hawaii International Conference on System Sciences
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
Proceedings of the 3rd conference on Computing frontiers
Classics in software engineering
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Proceedings of the 44th annual Design Automation Conference
Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems
EURASIP Journal on Embedded Systems
Aegis: A Single-Chip Secure Processor
IEEE Design & Test
From the bitstream to the netlist
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
A system architecture for reconfigurable trusted platforms
Proceedings of the conference on Design, automation and test in Europe
Physical unclonable function and true random number generator: a compact and scalable implementation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Authentication of FPGA bitstreams: why and how
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Securing embedded programmable gate arrays in secure circuits
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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A risk of covert insertion of circuitry into reconfigurable computing (RC) systems exists. This paper reviews risks of hardware attack on field programmable gate array (FPGA)-based RC systems and proposes a method for secure system credentials generation (unique, random and partially anonymous) and trusted self-reconfiguration, using a secure reconfiguration controller (SeReCon) and partial reconfiguration (PR). SeReCon provides a root of trust (RoT) for RC systems, incorporating novel algorithms for security credentials generation and trusted design verification. Credentials are generated internally, during system certification. The private credential element never leaves the SeReCon security perimeter. To provide integrity-maintaining self-reconfiguration, SeReCon performs analysis of each new IP core structure prior to reconfiguration. An unverified IP core can be used provided that its spatial isolation is retained. SeReCon provides encrypted storage for installed IP cores. Resource usage for a prototype SeReCon system is presented. The protection provided by SeReCon is illustrated in a number of security attack scenarios.