Communications of the ACM
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Alternate Wire Database for Xilinx FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
Proceedings of the 3rd conference on Computing frontiers
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
A dynamic reconfigurable hardware/software architecture for object tracking in video streams
EURASIP Journal on Embedded Systems
From the bitstream to the netlist
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
SeReCon: A Secure Dynamic Partial Reconfiguration Controller
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Managing Security in FPGA-Based Embedded Systems
IEEE Design & Test
A Protocol for Secure Remote Updates of FPGA Configurations
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
FPGA-Based Anomalous Trajectory Detection Using SOFM
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
SeReCon: a secure reconfiguration controller for self-reconfigurable systems
International Journal of Critical Computer-Based Systems
Parallel FPGA-based all-pairs shortest-paths in a directed graph
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially Reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools. This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic front-end allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by “recipe” scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system. The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs.