Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
IEEE Transactions on Computers
Design of Optimal Systolic Algorithms for the Transitive Closure Problem
IEEE Transactions on Computers
Journal of the ACM (JACM)
Communications of the ACM
Introduction to Algorithms
A blocked all-pairs shortest-paths algorithm
Journal of Experimental Algorithmics (JEA)
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Design Tradeoffs for BLAS Operations on Reconfigurable Hardware
ICPP '05 Proceedings of the 2005 International Conference on Parallel Processing
Automatic mapping of nested loops to FPGAS
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
The Journal of Supercomputing
Designing secure systems on reconfigurable hardware
ACM Transactions on Design Automation of Electronic Systems (TODAES)
All-pairs shortest-paths for large graphs on the GPU
Proceedings of the 23rd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Architectural support for multithreading on reconfigurable hardware
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Multithreading on reconfigurable hardware: An architectural approach
Microprocessors & Microsystems
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With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper, we propose a highly parallel FPGA design for the Floyd-Warshall algorithm to solve the allpairs shortest-paths problem in a directed graph. Our work is motivated by a computationally intensive bio-informatics application that employs this algorithm. The design we propose makes efficient and maximal utilization of the large amount of resources available on an FPGA to maximize parallelism in the presence of significant data dependences. Experimental results from a working FPGA implementation on the Cray XD1 show a speedup of 22 over execution on the XD1's processor.