Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform

Authors:
E. I. Milovanović;I. Ž Milovanović;M. P. Bekakos;I. N. Tselepis
Affiliations:
Faculty of Electronic Engineering, Niš, Serbia 18000;Faculty of Electronic Engineering, Niš, Serbia 18000;Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, Hellas, Greece;Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, Hellas, Greece
Venue:
The Journal of Supercomputing
Year:
2007

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Abstract

In this paper a regular bidirectional linear systolic array (RBLSA) for computing all-pairs shortest paths of a given directed graph is designed. The obtained array is optimal with respect to a number of processing elements (PE) for a given problem size. The execution time of the array has been minimized. To obtain RBLSA with optimal number of PEs, the accommodation of the inner computation space of the systolic algorithm to the projection direction vector is performed. Finally, FPGA-based reprogrammable systems are revolutionizing certain types of computation and digital logic, since as logic emulation systems they offer some orders of magnitude speedup over software simulation; herein, a FPGA realization of the RBLSA is investigated and the performance evaluation results are discussed.