Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays

Authors:
P. Z. Lee;Z. M. Kedem
Affiliations:
-;-
Venue:
IEEE Transactions on Parallel and Distributed Systems
Year:
1990

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Cited 21

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Abstract

Consideration is given to transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where 1or=qor=p-1. Previously, there existed complete characterizations of correct transformation only for the cases where q=p-1 orq=1. This gap is filled by giving formal necessary and sufficient conditions for correct transformation of a p-nested loop algorithm into a q-dimensional systolic array for any q,1or=qor=p-1. Practical methods are presented. The techniques developed are applied to the automatic design of special purpose and programmable systolic arrays. The results also contribute toward automatic compilation onto more general purpose programmable arrays. Synthesis of linear and planar systolic array implementations for a three-dimensional cube-graph algorithm and a reindexed Warshall-Floyd path-finding algorithm are used to illustrate the method.