The connection machine
Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Theory of linear and integer programming
Theory of linear and integer programming
VLSI array processors
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Systolic array synthesis: computability and time cones
Proceedings of the international workshop on Parallel algorithms & architectures
The systematic design of systolic arrays
Centre National de Recherche Scientifique on Automata networks in computer science: theory and applications
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Time Optimal Linear Schedules for Algorithms with Uniform Dependencies
IEEE Transactions on Computers
Optimization of Computation Time for Systolic Arrays
IEEE Transactions on Computers
Systematic generation of linear allocation functions in systolic array design
Journal of VLSI Signal Processing Systems
Some efficient solutions to the affine scheduling problem: I. One-dimensional time
International Journal of Parallel Programming
Linear mappings of n-dimensional uniform recurrences onto k-dimensional systolic arrays
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
The parallel execution of DO loops
Communications of the ACM
Parallel Programming and Compilers
Parallel Programming and Compilers
Parallel Computers Two: Architecture, Programming and Algorithms
Parallel Computers Two: Architecture, Programming and Algorithms
Introduction to VLSI Systems
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
On Loop Transformations for Generalized Cycle Shrinking
IEEE Transactions on Parallel and Distributed Systems
Constructive Methods for Scheduling Uniform Loop Nests
IEEE Transactions on Parallel and Distributed Systems
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
Partitioning Processor Arrays under Resource Constraints
Journal of VLSI Signal Processing Systems
A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures
Journal of VLSI Signal Processing Systems
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Many important algorithms in signal and image processingcan be described by uniform recurrences. A common method for thesynthesis of systolic arrays from uniform recurrences is based onspace-time transformations each of which consisting of two linearmappings, an allocation and a timing function. In this paper, weaddress the problem of finding space-time transformations which aretime-optimal or at least nearly time-optimal. For a given allocationfunction, a continuous relaxation of this problem is studied bypassing from linear to quasi-linear timing functions. A parametrizedlinear programming formulation is provided for finding quasi-lineartiming functions. The solution of each such linear problem, however,depends on the basis representation of the null space of theallocation function. Therefore, a branching approach is proposed forfinding quasi-linear timing functions which are optimal or have atleast low latency. It will be demonstrated by several large testexamples that branching into hundreds or even thousands of linearsubproblems can be computed with reasonable effort and often leads toan optimum linear timing function.