Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Theory of linear and integer programming
Theory of linear and integer programming
VLSI array processors
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Systolic array synthesis: computability and time cones
Proceedings of the international workshop on Parallel algorithms & architectures
The systematic design of systolic arrays
Centre National de Recherche Scientifique on Automata networks in computer science: theory and applications
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
The connection machine
Control generation in the design of processor arrays
Journal of VLSI Signal Processing Systems - Parallel processing on VLSI arrays
Time Optimal Linear Schedules for Algorithms with Uniform Dependencies
IEEE Transactions on Computers
Optimization of Computation Time for Systolic Arrays
IEEE Transactions on Computers
Systematic generation of linear allocation functions in systolic array design
Journal of VLSI Signal Processing Systems
Some efficient solutions to the affine scheduling problem: I. One-dimensional time
International Journal of Parallel Programming
Linear mappings of n-dimensional uniform recurrences onto k-dimensional systolic arrays
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
The parallel execution of DO loops
Communications of the ACM
Loop Parallelization
Parallel Programming and Compilers
Parallel Programming and Compilers
Parallel Computers Two: Architecture, Programming and Algorithms
Parallel Computers Two: Architecture, Programming and Algorithms
Introduction to VLSI Systems
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
On Loop Transformations for Generalized Cycle Shrinking
IEEE Transactions on Parallel and Distributed Systems
Constructive Methods for Scheduling Uniform Loop Nests
IEEE Transactions on Parallel and Distributed Systems
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP
Journal of VLSI Signal Processing Systems
A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures
Journal of VLSI Signal Processing Systems
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Many important algorithms can be described byn-dimensional uniform recurrences. The computations are thenindexed by integral vectors of length n and the datadependencies between computations can be described by thedifference vector of the corresponding indexes which areindependent of the indexes. This paper addresses the followingoptimization problem: Given an n-dimensional uniformrecurrence whose computation indexes are mapped by a linearfunction onto the processors of an array processor embedded ink-space (1≤ k ≤ n). Find an optimal linear functionfor the computation indexes. We study a continuousapproximation of this problem by passing from linear toquasi-linear timing functions. The resultant problemformulation is then a quadratic programming problem which can besolved by standard algorithms for quadratic or general nonlinearoptimization problems. We demonstrate the effectiveness of ourapproach by several nontrivial test examples.