Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Design of a Massively Parallel Processor
IEEE Transactions on Computers
STARAN parallel processor system hardware
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
A Signed Bit-Sequential Multiplier
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
Strategies for the Massively Parallel Simulation of Interconnection Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
VLSI Array Design Under Constraint of Limited I/O Bandwidth
IEEE Transactions on Computers
Application of the massively parallel processor to database management systems
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor
IEICE - Transactions on Information and Systems
Bit-Sequential Arithmetic for Parallel Processors
IEEE Transactions on Computers
Speeding-up successive Minkowski operations with bit-plane computers
Pattern Recognition Letters
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About a decade ago, a bit-serial parallel processing system STARAN®1 was developed. It used standard integrated circuits that were available at that time. Now, with the availability of VLSI, a much greater processing capability can be packed in a unit volume. This has led to the recent development of two bit-serial parallel processing systems: an airborne associative processor and a ground based massively parallel processor.