Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
An On-Line Square Root Algorithm
IEEE Transactions on Computers
IEEE Transactions on Computers
An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines
IEEE Transactions on Computers
IEEE Transactions on Computers
VLSI Performance Comparison of Banyan and Crossbar Communications Networks
IEEE Transactions on Computers
Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"
IEEE Transactions on Computers
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
On-Line Algorithms for Division and Multiplication
IEEE Transactions on Computers
Effective Pipelining of Digital Systems
IEEE Transactions on Computers
The Expression Processor: A Pipelined, Multiple- Processor Architecture
IEEE Transactions on Computers
On Division by Functional Iteration
IEEE Transactions on Computers
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output
IEEE Transactions on Computers
On Multiple Operand Addition of Signed Binary Numbers
IEEE Transactions on Computers
Comments on "Inner Product Computers"
IEEE Transactions on Computers
AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
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A bit-sequential processing element with O(n) complexity is described, where n is the wordlength of the operands. The operations performed by the element are A * B + C * D, A/B, and 驴A. The operands are fixed point or floating point numbers with variable precision. The concept of semi-on-line algorithms is introduced. A processing element that uses semi-on-line algorithms produces a result 驴 clock cycles after the absorption of the n-bit operands, where 驴 is small compared to n. In the paper the processing element and the algorithms are described. A performance comparison between the bit-sequential processing element and conventional pipelined arithmetic units is given.