Mesh Algorithms for Multiplication and Division
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
Bit-Sequential Arithmetic for Parallel Processors
IEEE Transactions on Computers
| Hi-index | 14.98 |
High-speed multifunction arithmetic arrays for multiplication, division, square and square-root operations are presented in this paper. These arrays seem attractive due to their versatility and speed. A recently described quotient-bit evaluation technique that uses the carry-save method in a nonuniform division array is extended here for the restoring-division process. This array includes the multiplication process as well, and the division time approaches that of multiplication. The design objective of multifunctional arithmetic arrays precludes consideration of other high-speed division techniques. A further extension of the restoring division process is shown to make the design of an array for square/square-root operation straightforward. The two underlying arrays can be coalesced to perform any one of the four operations. Possible methods of merging the arrays, with their relative merits, are also discussed. For illustration purposes, complete internal details of such a generalized pipelined array for 4-bit operation is included in this paper. Due consideration is also given to the possibility of large-scale integration of the different arrays illustrated in this paper.