Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
Efficient parallel circuits and algorithms for division
Information Processing Letters
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
IEEE Transactions on Computers - Special issue on computer arithmetic
The Montgomery Modular Inverse-Revisited
IEEE Transactions on Computers - Special issue on computer arithmetic
Synthesis of Parallel Algorithms
Synthesis of Parallel Algorithms
Systolic Modular Multiplication
IEEE Transactions on Computers
IEEE Transactions on Computers
On-Line Algorithms for Division and Multiplication
IEEE Transactions on Computers
Optimizing synchronous systems
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
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We consider the implementation of multiplication and division operations on one and two dimensional mesh of processors. We develop an O(驴n) step 2-dim mesh algorithm for multiplying two n-bit numbers. The algorithm is simple and does not rely upon discrete fourier transforms. We also develop an O(n) step 1-dim mesh algorithm for dividing a 2n-bit number by an n-bit number. This algorithm appears to be quite practical.