Designing systolic algorithms using sequential machines
IEEE Transactions on Computers - The MIT Press scientific computation series
A Study of Pipelining in Computing Arrays
IEEE Transactions on Computers
Mesh Algorithms for Multiplication and Division
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
Mirroring: a technique for pipelining semi-systolic and systolic arrays
Integration, the VLSI Journal
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On teaching fast adder designs: revisiting ladner & fischer
Theoretical Computer Science
Transformations of Timed Cooperating Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2000)
End-to-end latency computation in a multi-periodic design
Proceedings of the 28th Annual ACM Symposium on Applied Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we use crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of computationally useful networks. In particular, we describe 1) an N-node planar graph which has layout area ...