DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
EURO-DAC '94 Proceedings of the conference on European design automation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
SAT-Based Algorithms for Logic Minimization
ICCD '03 Proceedings of the 21st International Conference on Computer Design
AMUSE: a minimally-unsatisfiable subformula extractor
Proceedings of the 41st annual Design Automation Conference
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Proceedings of the 42nd annual Design Automation Conference
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
MUP: a minimal unsatisfiability prover
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Local-search Extraction of MUSes
Constraints
Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints
Journal of Automated Reasoning
Optimizing synchronous systems
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
Functionally linear decomposition and synthesis of logic circuits for FPGAs
Proceedings of the 45th annual Design Automation Conference
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
Interpolating functions from large Boolean relations
Proceedings of the 2009 International Conference on Computer-Aided Design
Searching for autarkies to trim unsatisfiable clause sets
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
A branch-and-bound algorithm for extracting smallest minimal unsatisfiable formulas
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Minimizing counterexample with unit core extraction and incremental SAT
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Deriving small unsatisfiable cores with dominators
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Discovery of minimal unsatisfiable subsets of constraints using hitting set dualization
PADL'05 Proceedings of the 7th international conference on Practical Aspects of Declarative Languages
A scalable algorithm for minimal unsatisfiable core extraction
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Extracting minimum unsatisfiable cores with a greedy genetic algorithm
AI'06 Proceedings of the 19th Australian joint conference on Artificial Intelligence: advances in Artificial Intelligence
A halting algorithm to determine the existence of decoder
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Towards completely automatic decoder synthesis
Proceedings of the International Conference on Computer-Aided Design
Inferring assertion for complementary synthesis
Proceedings of the International Conference on Computer-Aided Design
Synthesis of feedback decoders for initialized encoders
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.03 |
One of the most difficult jobs in designing communication and multimedia chips is to design and verify the complex complementary circuit pair (E, E-1), in which circuit E transforms information into a format suitable for transmission and storage, and its complementary circuit E-1 recovers this information. In order to facilitate this job, we proposed a novel two-step approach to synthesize the complementary circuit E-1 from E automatically. First, a SAT solver was used to check whether the input sequence of E can be uniquely determined by its output sequence. Second, the complementary circuit E-1 was built by characterizing its Boolean function, with an efficient all-solution SAT solver based on discovering XOR gates and extracting unsatisfiable cores. To illustrate its usefulness and efficiency, we ran our algorithm on several complex encoders from industrial projects, including PCIE and 10G Ethernet, and successfully built correct complementary circuits for them.