On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Synthesis of Communicating Processes from Temporal Logic Specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Deterministic generators and games for Ltl fragments
ACM Transactions on Computational Logic (TOCL)
A formal approach to the protocol converter problem
Proceedings of the conference on Design, automation and test in Europe
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
On synthesizing controllers from bounded-response properties
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Anzu: a tool for property synthesis
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach to design space exploration of protocol converters
Proceedings of the Conference on Design, Automation and Test in Europe
Rational behaviour and strategy construction in infinite multiplayer games
FSTTCS'06 Proceedings of the 26th international conference on Foundations of Software Technology and Theoretical Computer Science
A new algorithm for strategy synthesis in LTL games
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Synthesis of reactive(1) designs
VMCAI'06 Proceedings of the 7th international conference on Verification, Model Checking, and Abstract Interpretation
Minimizing counterexample of ACTL property
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
ACS: automatic converter synthesis for SoC bus protocols
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Towards completely automatic decoder synthesis
Proceedings of the International Conference on Computer-Aided Design
Inferring assertion for complementary synthesis
Proceedings of the International Conference on Computer-Aided Design
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Complementary synthesis automatically synthesizes the decoder circuit E−1 of an encoder E. It determines the existence of E−1 by checking the parameterized complementary condition (PC). However, this algorithm will not halt if E−1 does not exist. To solve this problem, we propose a novel halting algorithm to check PC in two steps. First, we over-approximate PC with the linear path unique condition (LP), and then falsify LP by searching for a loop-like path. If such a loop is found, then E−1 does not exist; otherwise, LP can eventually be proved within E's recurrence diameter. Second, with LP proved above, we construct a list of approximations that forms an onion-ring between PC and LP. The existence of E−1 can be proved by showing that E belongs to all these rings. To illustrate its usefulness, we have run our algorithm on several complex encoder circuits, including PCIE and 10G Ethernet. Experimental results show that our new algorithm always distinguishes correct Es from incorrect ones and halts properly.