The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Proof-guided underapproximation-widening for multi-process systems
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Checking consistency of C and Verilog using predicate abstraction and induction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A comparison of BDDs, BMC, and sequential SAT for model checking
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of SpecC using predicate abstraction
Formal Methods in System Design
Compressing BMC Encodings with QBF
Electronic Notes in Theoretical Computer Science (ENTCS)
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Completeness in SMT-based BMC for software programs
Proceedings of the conference on Design, automation and test in Europe
Bounded Semantics of CTL and SAT-Based Verification
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Computing Over-Approximations with Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT-based verification of LTL formulas
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Experimental analysis of different techniques for bounded model checking
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
SAT-based summarization for Boolean programs
Proceedings of the 14th international SPIN conference on Model checking software
Model checking with SAT-based characterization of ACTL formulas
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
A complete bounded model checking algorithm for pushdown systems
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Diagnosing Process Trajectories Under Partially Known Behavior
Proceedings of the 2010 conference on ECAI 2010: 19th European Conference on Artificial Intelligence
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A halting algorithm to determine the existence of decoder
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design
Inferring assertion for complementary synthesis
Proceedings of the International Conference on Computer-Aided Design
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Bounded satisfiability checking of metric temporal logic specifications
ACM Transactions on Software Engineering and Methodology (TOSEM) - In memoriam, fault detection and localization, formal methods, modeling and design
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SAT based Bounded Model Checking (BMC) is an efficient method for detecting logical errors in finite-state transition systems. Given a transition system, an LTL property, and a user defined bound k, a bounded model checker generates a propositional formula that is satisfiable if and only if a counterexample to the property of length up to k exists. Standard SAT checkers can be used to check this formula. BMC is complete if k is larger than some pre-computed threshold. It is still unknown how to compute this threshold for general properties. We show that the longest initialized loop-free path in the state graph, also known as the recurrence diameter, is sufficient for Fp properties. The recurrence diameter is also a known over-approximation for the threshold of simple safety properties (Gp). We discuss various techniques to compute the recurrence diameter efficiently and provide experimental results that demonstrate the benefits of using the new approach.