Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Model checking
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Stochastic Colored Petri Net Models for Rainbow Optical Networks
Application of Petri Nets to Communication Networks, Advances in Petri Nets
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Successive Approximation of Abstract Transition Relations
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Checking consistency of C and Verilog using predicate abstraction and induction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT-based sequential depth computation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Automatic error finding in access-control policies
Proceedings of the 18th ACM conference on Computer and communications security
Mohawk: Abstraction-Refinement and Bound-Estimation for Verifying Access Control Policies
ACM Transactions on Information and System Security (TISSEC)
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Bounded Model Checking (BMC) searches for counterexamples to a property @f with a bounded length k. If no such counterexample is found, k is increased. This process terminates when k exceeds the completeness threshold CT (i.e., k is sufficiently large to ensure that no counterexample exists) or when the SAT procedure exceeds its time or memory bounds. However, the completeness threshold is too large for most practical instances or too hard to compute. Hardware designers often modify their designs for better verification and testing results. This paper presents an automated technique based on cut-point insertion to obtain an over-approximation of the model that 1) preserves safety properties and 2) has a CT which is small enough to actually prove @f using BMC. The algorithm uses proof-based abstraction refinement to remove spurious counterexamples.