Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Incremental CTL model checking using BDD subsetting
DAC '98 Proceedings of the 35th annual Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Symbolic Model Checking
Counterexample-guided choice of projections in approximate symbolic model checking
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
An Iterative Approach to Language Containment
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Automatic state space decomposition for approximate FSM traversal based on circuit analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hybrid verification approach: getting deep into the design
Proceedings of the 39th annual Design Automation Conference
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Stochastic Colored Petri Net Models for Rainbow Optical Networks
Application of Petri Nets to Communication Networks, Advances in Petri Nets
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic abstraction and verification of verilog models
Proceedings of the 41st annual Design Automation Conference
Abstraction refinement by controllability and cooperativeness analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Word level predicate abstraction and refinement for verifying RTL verilog
Proceedings of the 42nd annual Design Automation Conference
Dynamic abstraction using SAT-based BMC
Proceedings of the 42nd annual Design Automation Conference
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reconsidering CEGAR: Learning Good Abstractions without Refinement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Compositional SCC Analysis for Language Emptiness
Formal Methods in System Design
Automatic assume guarantee analysis for assertion-based formal verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Highlevel verification of control intensive systems using predicate abstraction
Formal methods and models for system design
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
A novel collaborative scheme of simulation and model checking for system properties verification
Computers in Industry - Special issue: Collaborative environments for concurrent engineering
Proceedings of the conference on Design, automation and test in Europe
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
A novel formal verification approach for RTL hardware IP cores
Computer Standards & Interfaces
Computing Over-Approximations with Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Interleaved invariant checking with dynamic abstraction
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
GLA: gate-level abstraction revisited
Proceedings of the Conference on Design, Automation and Test in Europe
Core minimization in SAT-based abstraction
Proceedings of the Conference on Design, Automation and Test in Europe
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We present RFN, a formal property verification tool based on abstraction refinement. Abstraction refinement is a strategy for property verification. It iteratively refines an abstract model to better approximate the behavior of the original design in the hope that the abstract model alone will provide enough evidence to prove or disprove the property.However, previous work on abstraction refinement was only demonstrated on designs with up to 500 registers. We developed RFN to verify real-world designs that may contain thousands of registers. RFN differs from the previous work in several ways. First, instead of relying on a single engine, RFN employs multiple formal verification engines, including a BDD-ATPG hybrid engine and a conventional BDD-based fixpoint engine, for finding error traces or proving properties on the abstract model. Second, RFN uses a novel two-phase process involving 3-valued simulation and sequential ATPG to determine how to refine the abstract model. Third, RFN avoids the weakness of other abstraction-refinement algorithms --- finding error traces on the original design, by utilizing the error trace of the abstract model to guide sequential ATPG to find an error trace on the original design.We implemented and applied a prototype of RFN to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results. On these designs, we successfully proved a few properties and discovered a design violation.