Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Dynamic abstraction using SAT-based BMC
Proceedings of the 42nd annual Design Automation Conference
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
Test case generation from formal models through abstraction refinement and model checking
Proceedings of the 3rd international workshop on Advances in model-based testing
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Constraints in one-to-many concretization for abstraction refinement
Proceedings of the 46th Annual Design Automation Conference
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A counterexample-guided abstraction-refinement framework for markov decision processes
ACM Transactions on Computational Logic (TOCL)
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Interleaved invariant checking with dynamic abstraction
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Efficient coverage of parallel and hierarchical stateflow models for test case generation
Software Testing, Verification & Reliability
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In this paper, we present a method for finding failure traces for safety properties that are out of reach for traditional approaches to counter example generation. We do this by guiding Bounded Model Checking (BMC) with information gathered from counter example guided abstraction refinement. Unlike previously described approaches based on reconstructing abstract counter examples on the concrete machines, we do not limit ourselves to search for failures of the same length as the current abstract counterexample. We also describe a combination of previously known methods for choosing registers to include in the abstraction that we have found works very well together with our technique for finding failures. Our experimental results show that the resulting method can find counter examples that are out ofrange for both standard BMC and two previously published approaches to abstraction-guided BMC.