High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An automata-theoretic approach to linear temporal logic
Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency : structure versus automata: structure versus automata
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid verification using saturated simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Probabilistic state space search
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic lighthouse generation for directed state space search
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Rarity based guided state space search
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Symbolic Model Checking
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Simplifying Boolean constraint solving for random simulation-vector generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient LTL compilation for SAT-based model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Stimulus generation for constrained random simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Random stimulus generation using entropy and XOR constraints
Proceedings of the conference on Design, automation and test in Europe
Towards efficient sampling: exploiting random walk strategies
AAAI'04 Proceedings of the 19th national conference on Artifical intelligence
A lightweight component caching scheme for satisfiability solvers
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
Generating diverse solutions in SAT
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
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Semiformal, or hybrid, verification techniques are extensively used in pre-silicon hardware verification. Most approaches combine simulation and formal verification (FV) algorithms to achieve better design coverage than conventional simulation and scale better than FV. In this paper we introduce a purely SAT-based semiformal verification (SFV) method that is based on new algorithms for generating multiple heterogeneous models for a propositional formula. An additional novelty of our paper is the extension of the SFV algorithm to liveness properties. The experimental data presented in this paper clearly shows that the proposed method can effectively find bugs in complex industrial designs that neither simulation nor FV reveal.