A Scalable Parallel Algorithm for Reachability Analysis of Very Large Circuits
Formal Methods in System Design
Efficient Debugging in a Formal Verification Environment
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Integrating BDD-Based and SAT-Based Symbolic Model Checking
FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Combining symmetry reduction and under-approximation for symbolic model checking
Formal Methods in System Design
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
GSTE is partitioned model checking
Formal Methods in System Design
Fifteen Years of Formal Property Verification in Intel
25 Years of Model Checking
Survey on Directed Model Checking
Model Checking and Artificial Intelligence
ACM Computing Surveys (CSUR)
Language-Emptiness Checking of Alternating Tree Automata Using Symbolic Reachability Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Abstraction and refinement in model checking
FMCO'05 Proceedings of the 4th international conference on Formal Methods for Components and Objects
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Symbolic systems, explicit properties: on hybrid approaches for LTL symbolic model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Achieving speedups in distributed symbolic reachability analysis through asynchronous computation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Abstraction-Guided model checking using symbolic IDA* and heuristic synthesis
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
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