Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Binary decision diagrams on network of workstation
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Distributed Binary Decision Diagrams for Verification of Large Circuit
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Parallelizing the Murphi Verifier
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Implementing Remote procedure calls
SOSP '83 Proceedings of the ninth ACM symposium on Operating systems principles
Improving the efficiency of BDD-based operators by means of partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Distributed Symbolic Model Checking for μ-Calculus
Formal Methods in System Design
A work-efficient distributed algorithm for reachability analysis
Formal Methods in System Design
Dealing with practical limitations of distributed timed model checking for timed automata
Formal Methods in System Design
GSTE is partitioned model checking
Formal Methods in System Design
Hybrid BDD and All-SAT Method for Model Checking
Languages: From Formal to Natural
Parallel disk-based computation for large, monolithic binary decision diagrams
Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Achieving speedups in distributed symbolic reachability analysis through asynchronous computation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a scalable method for parallelizing symbolic reachability analysis on a distributed-memory environment of workstations. We have developed an adaptive partitioning algorithm that significantly reduces space requirements. The memory balance is maintained by dynamically repartitioning the state space throughout the computation. A compact BDD representation allows coordination by shipping BDDs from one machine to another. This representation allows for different variable orders in the sending and receiving processes. The algorithm uses a distributed termination protocol, with none of the memory modules preserving a complete image of the set of reachable states. No external storage is used on the disk. Rather, we make use of the network, which is much faster.We implemented our method on a standard, loosely-connected environment of workstations, using a high-performance model checker. Initial performance evaluation of several large circuits shows that our method can handle models too large to fit in the memory of a single node. The partitioning algorithm achieves reduction in space, which is linear in the number of workstations employed. A corresponding decrease in space requirements is measured throughout the reachability analysis. Our results show that the relatively slow network does not become a bottleneck, and that computation time is kept reasonably small.