Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Complexity of Equivalence and Containment for Free Single Variable Program Schemes
Proceedings of the Fifth Colloquium on Automata, Languages and Programming
Decomposition Techniques for Efficient ROBDD Construction
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
An improved data parallel algorithm for Boolean function manipulation using BDDs
PDP '95 Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing
A study of composition schemes for mixed apply/compose based construction of ROBDDs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
Sampling schemes for computing OBDD variable orderings
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient filter-based approach for combinational verification
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Analysis of composition complexity and how to obtain smaller canonical graphs
Proceedings of the 37th Annual Design Automation Conference
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Formal Methods in System Design
Automatic partitioning for efficient combinatorial verification
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A note on complexity of OBDD composition and efficiency of partitioned-OBDDs over OBDDs: 1289
IEEE Transactions on Computers
The future of logic synthesis and verification
Logic Synthesis and Verification
A Comparison of Free BDDs and Transformed BDDs
Formal Methods in System Design
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Scalable Parallel Algorithm for Reachability Analysis of Very Large Circuits
Formal Methods in System Design
A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs
IEEE Transactions on Computers
Scalable Distributed On-the-Fly Symbolic Model Checking
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
BDDs: design, analysis, complexity, and applications
Discrete Applied Mathematics - Optimal discrete structure and algorithms (ODSA 2000)
Improved symbolic simulation by functional-space decomposition
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast Computation of Data Correlation Using BDDs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient Preimage Computation Using A Novel Success-Driven ATPG
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Distributed Symbolic Model Checking for μ-Calculus
Formal Methods in System Design
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Fast falsification based on symbolic bounded property checking
Proceedings of the 43rd annual Design Automation Conference
A work-efficient distributed algorithm for reachability analysis
Formal Methods in System Design
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
GSTE is partitioned model checking
Formal Methods in System Design
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDDs-design, analysis, complexity, and applications
Discrete Applied Mathematics
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Distributed Symbolic Bounded Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
The computational complexity of equivalence and isomorphism problems
The computational complexity of equivalence and isomorphism problems
Parallel disk-based computation for large, monolithic binary decision diagrams
Proceedings of the 4th International Workshop on Parallel and Symbolic Computation
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
On partitioning and symbolic model checking
FM'05 Proceedings of the 2005 international conference on Formal Methods
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We present a new representation for Boolean functions called Partitioned ROBDDs. In this representation we divide the Boolean space into 'k' partitions and represent a function over each partition as a separate ROBDD. We show that partitioned-ROBDDs are canonical and can be efficiently manipulated. Further they can be exponentially more compact than monolithic ROBDDs and even free BDDs. Moreover, at any given time, only one partition needs to be manipulated which further increases the space efficiency. In addition to showing the utility of partitioned-ROBDDs on special classes of functions, we provide automatic techniques for their construction. We show that for large circuits our techniques are more efficient in space as well as time over monolithic ROBDDs. Using these techniques, some complex industrial circuits could be verified for the first time.