Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient breadth-first manipulation of binary decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Efficient OBDD-based boolean manipulation in CAD beyond current limits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Extracting RTL models from transistor netlists
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
High performance BDD package by exploiting memory hierarchy
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Discrete Mathematics in Computer Science
Discrete Mathematics in Computer Science
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Complexity of Equivalence and Containment for Free Single Variable Program Schemes
Proceedings of the Fifth Colloquium on Automata, Languages and Programming
Decomposition Techniques for Efficient ROBDD Construction
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of Arithmetic Circuits by Comparing Two Similar Circuits
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A study of composition schemes for mixed apply/compose based construction of ROBDDs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
IEEE Transactions on Computers
Some heuristics for generating tree-like FBDD types
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Comparing layouts with HDL models: a formal verification technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic formal verification of DSP software
Proceedings of the 37th Annual Design Automation Conference
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Translation among CNFs, characteristic models and ordered binary decision diagrams
Information Processing Letters
Cutpoints for formal equivalence verification of embedded software
Proceedings of the 5th ACM international conference on Embedded software
Proceedings of the 43rd annual Design Automation Conference
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
IEEE Transactions on Computers
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
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With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. In this paper we survey some state-of-the-art techniques used to perform automatic verification of combinational circuits. We classify the current approaches for combinational verification into two categories functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. We briefly describe some of the methods in both the categories and discuss their merits and drawbacks.