Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic computation of logic implications for technology-dependent low-power synthesis
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An efficient filter-based approach for combinational verification
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
An Efficient Logic Equivalence Checker for Industrial Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Automatic partitioning for efficient combinatorial verification
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table
Formal Methods in System Design
On a Model-Based Design Verificationfor Combinatorial Boolean Networks
IEA/AIE '02 Proceedings of the 15th international conference on Industrial and engineering applications of artificial intelligence and expert systems: developments in applied artificial intelligence
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
On More Efficient Combinational ATPG Using Functional Learning
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A BDD-based verification method for large synthesized circuits
Integration, the VLSI Journal
Partial synthesis through sampling with and without specification
Proceedings of the International Conference on Computer-Aided Design
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