Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Equivalence checking of integer multipliers
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Verification of Arithmetic Circuits by Comparing Two Similar Circuits
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Implicit Verification of Structurally Dissimilar Arithmetic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Arithmetic Reasoning in DPLL-Based SAT Solving
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving constant-coefficient multiplier verification by partial product identification
Proceedings of the conference on Design, automation and test in Europe
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.