Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
LPSAT: a unified approach to RTL satisfiability
Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Functional Test Generation using Constraint Logic Programming
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
A fast pseudo-boolean constraint solver
Proceedings of the 40th annual Design Automation Conference
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
Applications of SAT solvers to cryptanalysis of hash functions
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
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We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level description of the arithmetic circuit parts and the property. This description can easily be provided by the front-end of an RTL property checker. The calculus yields significant speedup and more robustness on hard SAT instances derived from the formal verification of arithmeticcircuits.