On automatic generation of RTL validation test benches using circuit testing techniques
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Arithmetic Reasoning in DPLL-Based SAT Solving
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Assertion-based automated functional vectors generation using constraint logic programming
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Normalization at the arithmetic bit level
Proceedings of the 42nd annual Design Automation Conference
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure
Proceedings of the 44th annual Design Automation Conference
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Algorithm for VHDL Parallel Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding two disjoint paths in a network with normalized α+-MIN-SUM objective function
ISAAC'05 Proceedings of the 16th international conference on Algorithms and Computation
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Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic, and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satisfiability (SAT) checking problem by expanding the arithmetic modules into logic gates. However, this approach is not very efficient. We present a new HDL-SAT checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of data-path modules and SAT checking for logic equations that govern the behavior of control modules. This feature is critically important to efficiency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-SAT checking algorithm in this paper. Experimental results that show significant speedups over state-of-the-art gate-level SAT checking methods are included