RTL SAT simplification by Boolean and interval arithmetic reasoning

Authors:
G. Parthasarathy;M. K. Iyer;K.-T. Cheng;F. Brewer
Affiliations:
California Univ., Santa Barbara, CA, USA;California Univ., Santa Barbara, CA, USA;California Univ., Santa Barbara, CA, USA;California Univ., Santa Barbara, CA, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

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Abstract

We present a method that combines interval-arithmetic (IA) and Boolean reasoning with structural hashing for simplifying SAT problems on circuits expressed at the register-transfer level. We demonstrate that simple transformations based on interval-arithmetic operations can significantly reduce the complexity of the problem. We identify cases where the inherent over-approximations in IA operations can be reduced. We demonstrate that these techniques can significantly reduce RTL-SAT instances in size and runtime.