GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
A machine program for theorem-proving
Communications of the ACM
Interval arithmetic: From principles to implementation
Journal of the ACM (JACM)
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
CVC: A Cooperating Validity Checker
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
Proceedings of the 40th annual Design Automation Conference
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An efficient finite-domain constraint solver for circuits
Proceedings of the 41st annual Design Automation Conference
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL SAT simplification by Boolean and interval arithmetic reasoning
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Predicate learning and selective theory deduction for a difference logic solver
Proceedings of the 43rd annual Design Automation Conference
EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure
Proceedings of the 44th annual Design Automation Conference
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We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending concepts from classic automatic test-pattern generation (ATPG) algorithms and interval-arithmetic to guide the search process. We extend the idea of Boolean recursive learning on predicate logic in the RTL using Boolean and interval constraint propagation in the control and data-path of the circuit. This is used as a pre-processing step to derive relations between predicate logic signals that are used to augment the search. We demonstrate experimentally that these methods provide significant improvement over current techniques on sample benchmarks.