A transitive closure based algorithm for test generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Implication graph based domino logic synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Multi-node static logic implications for redundancy identification
DATE '00 Proceedings of the conference on Design, automation and test in Europe
False-Path Removal Using Delay Fault Simulation
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
A framework for low complexitgy static learning
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Structural search for RTL with predicate learning
Proceedings of the 42nd annual Design Automation Conference
A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Fast illegal state identification for improving SAT-based induction
Proceedings of the 43rd annual Design Automation Conference
Mining global constraints for improving bounded sequential equivalence checking
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Computers
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
Small-delay defect detection in the presence of process variations
Microelectronics Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper presents a new static logic implication algorithm. An improved implication procedure that fully takes advantage of the special context of static implication, the iterative method, and set algebra is described. The algorithm discovers at low cost many indirect implications which are not discovered by dynamic learning without tremendous time cost. The experimental results show that a very large number of indirect implications are found by our algorithm. The static implication procedure has many useful applications, one of which is static redundancy identification. Use of the static implications obtained from the algorithm in static redundancy identification for ISCAS85 combinational circuits resulted in a larger number of redundant faults identified than in previous methods.