Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Identification and Test Generation for Primitive Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Test Generator for Segment Delay Faults
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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The number of robustly testable paths is very low for typicalcircuits, hence the delay defect coverage of a robustpath fault test set can be very small. Robustly testing path-segments which are not covered by any robustly testablepaths can enhance the defect coverage of a path test set,however the existence of such uncovered path-segments inbenchmark circuits has not been proven so far. In this paperwe experimentally prove the existence of robustly testablepath-segments not covered by any robustly testable pathsin the ISCAS benchmark circuits. A highly effective delayfault test generator, using some novel techniques, has beenimplemented for this purpose and is also described in thepaper.