A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Design for testability for path delay faults in sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Delay-Verifiability of Combinational Circuits Based on Primitive Faults
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Generation of high quality tests for functional sensitizable paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient diagnosis of path delay faults in digital logic circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Performance sensitivity analysis using statistical method and its applications to delay
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Path delay fault testing using test points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Invalidation Mechanisms for Non-Robust Delay Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Design for Primitive Delay Fault Testability
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Generalized Sensitization using Fault Tuples
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Non-Enumerative Path Delay Fault Diagnosis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems
IEEE Transactions on Computers
The coupling model for function and delay faults
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
a fuzzy model for path delay fault detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
In many designs a large portion of path delay faults is not robustly testable. In this paper, we investigate testing strategies for robustly untestable faults. We show that the quality of nonrobust tests may be very poor in detecting small defects caused by manufacturing process variation. We demonstrate that better quality nonrobust tests can be obtained by including timing information into the process of test generation. A good nonrobust test can tolerate larger timing variations on the off-inputs. We also show that not all nonrobustly untestable path delay faults may be ignored in high quality delay testing. Functional sensitizable paths are nonrobustly untestable but, under some faulty conditions, may degrade the performance of the circuit. However, up till now, there was no strategy for generating tests for such faults.In this paper, we present algorithms for generating high quality nonrobust and functional sensitizable tests. We also devise an algorithm for generating tests for validatable nonrobust faults which have a high quality in detecting defects but are hard to be generated automatically. Our experimental results show that the quality of delay testing increases if validatable and high quality nonrobust tests, as well as tests for functional sensitizable path delay faults are included.