Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Generation of high quality non-robust tests for path delay faults
DAC '94 Proceedings of the 31st annual Design Automation Conference
Path hashing to accelerate delay fault simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Testable path delay fault cover for sequential circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Modeling and simulation of real defects using fuzzy logic
Proceedings of the 37th Annual Design Automation Conference
Integrated test of interacting controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
Functionally Testable Path Delay Faults on a Microprocessor
IEEE Design & Test
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Primitive Path Delay Fault Identification
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
(Quasi-) Linear Path Delay Fault Tests for Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Flexible Path Selection Procedure for Path Delay Fault Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Design for Primitive Delay Fault Testability
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
On effective criterion of path selection for delay testing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Exploring linear structures of critical path delay faults to reduce test efforts
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input necessary assignments for testing of path delay faults in standard-scan circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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