Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic optimization by an improved sequential redundancy addition and removal techniques
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Delay-Verifiability of Combinational Circuits Based on Primitive Faults
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Generation of high quality tests for functional sensitizable paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
| Hi-index | 0.00 |
Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs could be very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths. Our results show that it is possible to obtain circuits with a significant reduction in the number of paths while not increasing area and/or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points can help reducing the number of such paths in the given design.