Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Is redundancy necessary to reduce delay
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Circuit structure relations to redundancy and delay: the KMS algorithm revisited
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Circuit enhancement by eliminating long false paths
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On local transformations and path delay fault testability
Journal of Electronic Testing: Theory and Applications
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Local Transformations and Robust Dependent Path Delay
Proceedings of the IEEE International Test Conference on Test and Design Validity
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability
Proceedings of the IEEE International Test Conference on Test and Design Validity
Achieving Complete Delay Fault Testability by Extra Inputs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
| Hi-index | 0.00 |
It has been shown previously, that paths which are internally fanout free and not non-robustly testable with respect to at least one transition, can be removed from a circuit without changing its functional behavior. This transformation has been successfully applied in order to remove long false paths from a given circuit. In this work, we show how to apply the above transformation in order to improve delay testability. Experimental results demonstrate that large improvements in testability can be obtained at low hardware costs. In addition, the delay of the circuits is even reduced in most cases.