Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Extended stuck-fault testability for combinational networks
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Performance and testability interactions in logic synthesis
Performance and testability interactions in logic synthesis
A symbolic method to reduce power consumption of circuits containing false paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance optimization using exact sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Elimination of multi-cycle false paths by state encoding
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Functional clock schedule optimization
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
| Hi-index | 0.00 |